1. Field of the Invention
The present invention relates to simulation for analyzing electric circuit behavior in an electric circuit.
2. Description of the Related Art
Various evaluations and tests are performed during a test production of an electric circuit to be mounted on an electronic apparatus. An example of such an evaluation is to verify the safety of the electric circuit. This testing is to verify whether safety can be guaranteed even when a component mounted on the electric circuit fails. Specifically, this testing verifies whether an abnormality will occur in another component when the component short-circuits or open-circuits.
This testing has to verify the behavior of the circuit by pseudo-causing the components to fail one by one. Since an operation for setting this pseudo-failed state has to be performed for all of the components constituting the electric circuit, this takes a lot of time. Further, the testing can be wrongly performed due to setting mistakes or lapses. Therefore, a failure analysis method based on circuit simulation has been proposed.
Japanese Patent Application Laid-Open No. 9-319777 discusses an electric circuit failure analysis method which, when a constituent element of an electric circuit has short-circuited or open-circuited, can analyze whether an abnormality will occur in other constituent elements of the electric circuit. More specifically, this method generates a net list of the constituent elements in the electric circuit which have short-circuited or open-circuited, and analyzes the net list. Then, the method compares the analysis result of each constituent element and a prescribed value for each constituent element, and determines whether an abnormality will occur if the analysis result exceeds the prescribed information. The test location and the constituent elements for which it was determined that an abnormality would occur are displayed by flashing. Consequently, just by inputting the circuit information, a user can automatically perform the test, thereby reducing the actual time required for testing. Further, since all settings are automatically tested by an information arithmetic processing apparatus, the testing can be performed more accurately and without lapses as compared with when performed by hand.
Thus, in the electric circuit failure analysis method discussed in Japanese Patent Application Laid-Open No. 9-319777, when a component, which is a constituent element of the electric circuit, has short-circuited or open-circuited, the method analyzes whether an abnormality will occur in the other components. However, component failure is not only due to short-circuiting or open-circuiting. Component failure can also be caused by a component failing while retaining a certain resistance (hereinafter, “half short-circuit”). In such a case, since the abnormality occurs in the failed component itself due to power consumption, testing also needs to be performed for cases in which a half short-circuit has occurred.
However, since the resistance value when a component has half short-circuited varies depending on how the component failed, the power consumption cannot be calculated. Therefore, the testing has to be performed by pseudo-half short-circuiting the component by changing the resistance value of the component to be half short-circuited to a different resistance several times. Consequently, the resistance setting operation takes a very long time. Further, the determination of the resistance values relies on the tester, so that determination mistakes and testing lapses can occur.
To resolve the above-described problems, the resistance during a half short-circuit needs to be calculated. The resistance when a half short-circuit occurs is not a resistance which reproduces the variance caused by how the component failed, but has to be a resistance which includes such variances. This is because calculating a resistance which reproduces a given failed state does not mean that verification could be performed which includes all the individual differences used in mass production. It must be verified that an abnormality state will not occur for all failed states. Further, the reason why an abnormality occurs in a half short-circuited component is that current flows to a failed resistor, thereby causing abnormal heat generation due to power being consumed.
Therefore, to resolve the above-described problems, it is necessary to calculate the resistance value and the power consumption of a component when that component has half short-circuited.